1. Field of the Invention
This invention relates generally to computer systems and associated hardware, and particularly to methods and apparatuses for facilitating testing of integrated circuit devices.
2. Description of the Related Art
Electronic devices, such as computer chips, can include multiple and often thousands of logic circuits. To ensure that the logic circuits are operating correctly before they are put to use, these circuits are tested to verify wiring integrity. To facilitate this testing, during fabrication flip-flops are configured with multiplexers to form scan-flops. As is shown in FIG. 1, a scan-flop 10 includes a flip-flop 12 electrically connected to a multiplexer (MUX) 14. A data-in signal (DI) and a scan-in signal (SI) are input to the MUX 14 along with a scan-enable signal (SE). An output is passed from the MUX 14 to the flip-flop 12 through an electrical connection 16, to provide a data signal D to the flip-flop 12. A clock signal CLK is also passed to the flip-flop 12. Thus, with the clock signal CLK and data signal D, the flip-flop 12 generates an output signal Q and an output signal NQ which is the inverse of Q.
Scan-flops such as that shown in FIG. 1 are then electrically connected to each other in series to form a scan chain, in a process sometimes referred to as scan chain stitching. Other non-scan logic circuitry (miscellaneous logic) that is to be tested by the scan mode testing, is also electrically connected to the scan chain, interspersed between various scan-flops. For example, FIG. 2 depicts a representative scan chain 20. A scan-flop 10 is connected to miscellaneous logic 24, which is desired to be tested with the scan chain 20. Another scan-flop 10' is connected to miscellaneous logic 24 to complete the scan chain. Of course, other miscellaneous logic and other scan-flops can be included in the scan chain 20. In particular, other miscellaneous logic 26 is connected to scan-flop 10, as well as to other miscellaneous logic or scan-flop of another scan-chain (not shown).
Signals, in the form of a test vector, can be passed through the scan chain 20 to test the miscellaneous logic by monitoring the output signal. Typically the test vector is introduced to the scan chain as the scan-in signal SI of the first scan-flop 10 of the scan chain 20. Scan signals 22, including a scan-in signal SI, scan-enable signal SE, and clock signal CLK, are shown introduced to the scan flops 10 and 10' of the scan chain 20. The test vector is sequentially shifted into each scan-flop of the scan chain, in accordance with the clock signal CLK. After the test vector is passed into the miscellaneous logic from adjacent scan-flops, the scan-flops are sequentially unloaded to an output signal SO. This output signal SO is then analyzed to verify the wiring and functionality of the miscellaneous logic that is electrically connected to the scan chain. For example, the output signal can be compared to an output signal that would be expected, given the known scan chain path, miscellaneous logic, and test vector, with any differences being indicative of a possible fault in the miscellaneous logic circuitry. In addition, the inverse output signals NQ and NQ' of the scan-flops 10 and 10' can be passed to other circuitry such as miscellaneous logic 26 or scan-flops of other scan chains (not shown).
As is well known, in order to load the test vector into the scan chain 20 to initiate testing, the test vector data must be sequentially loaded into each scan flop 20. Unfortunately, the longer the scan chain is, the longer the time to test the device. This is because loading each individual scan-flop with the test vector requires one clock. Accordingly, this sequential loading and unloading of all of the scan-flops each entail a number of clocks equal to the number of scan-flops, which can be in the order of thousands. The greater this test time is, the lower the production yield, and therefore the lower the production output. Therefore, in order to minimize the impact of testing on production output, test time can be limited by limiting the size of the scan chains during the design phase. Thus, rather than having a single scan chain of several thousand scan-flops, multiple scan chains that can be run in parallel may be used, each with a certain desired maximum number of scan-flops.
While two scan-flops 10 and 10' are depicted in the scan chain 20 of FIG. 2, a typical scan chain can encompass thousands of scan-flops 10. Typically, the particular scan path of a scan chain 20 can be designed using a synthesis tool, such as Synopsys which can be obtained from Synopsys, Inc. of Mountain View, Calif. Information regarding operational and other aspects of Synopsys can be found in "About Synopsys Online Documentation--Version 1998.02," which is incorporated herein by reference. Such a tool is utilized to identify which scan-flops are to be included within a particular scan chain, to determine the particular scan path that is to be formed between both scan-flops 10 and the miscellaneous logic that is to be tested, and to physically stitch the scan chain. Unfortunately, such tools require a user to manually input each register that is to be included on a single scan chain. This manual designation includes manually counting each scan-flop and identifying it as being within the scan chain. As the number of scan-flops increases, the error rate in designated these scan-flops can become increasingly burdensome and prone to error. This problem is further exacerbated by increasing circuit densities on IC devices.
Thus, it is desired to have a method and system for creating multiple scan chains having varying numbers of scan-flops, within a single design, while minimizing error rates and design time.